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Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /ANA_CTL0

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Interpret as ANA_CTL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CSLDAC 0 (VCC_SEL)VCC_SEL 0 (FLIP_AMUXBUS_AB)FLIP_AMUXBUS_AB

Description

Analog control 0

Fields

CSLDAC

Trimming of common source line DAC.
VCC_SEL

Vcc select: ‘0’: 1.2 V : LP reset value ‘1’: 0.95 V: ULP reset value Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field.
FLIP_AMUXBUS_AB

Flips amuxbusa and amuxbusb ‘0’: amuxbusa, amuxbusb ‘1’: amuxbusb, amuxbusb

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data